VLSI TOPICS

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS

A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications

A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications

Approximate Sum-of-Products Designs Based on Distributed Arithmetic

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability

The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection

A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme

A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation

A Fast-Locking, Low-Jitter Pulsewidth Control Loop for High-Speed ADC

A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution

A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition

Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design

Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing

An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers

Basic-Set Trellis Min–Max Decoder Architecture for Non binary LDPC Codes With High- Order Galois Fields

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction

Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method

Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy

Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits

An Energy-Efficient Programmable Many core Accelerator for Personalized Biomedical Applications

VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems

A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging

Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption

Resource-Efficient SRAM-based Ternary Content Addressable Memory

Write-Amount-Aware Management Policies for STT-RAM Caches

Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA

High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder

High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

Efficient Designs of Multi-ported Memory on FPGA

High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock

A 2.4–3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique

Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares

Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm

A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission

Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares

VLSI Design of 64bit × 64bit High Performance Multiplier with Redundant Binary Encoding

ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware

Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs

Efficient Soft Cancelation Decoder Architectures for Polar Codes

Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix–Vector Product Decomposition

Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication

FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers

Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields

Antiwear Leveling Design for SSDs With Hybrid ECC Capability

Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding

RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy- Efficient Digital Signal Processing

Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations

Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

An FPGA-Based Hardware Accelerator for Traffic Sign Detection

Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations

Time-Encoded Values for Highly Efficient Stochastic Circuits

Design of Power and Area Efficient Approximate Multipliers

COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction

Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures

Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique

10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

Delay Analysis for Current Mode Threshold Logic Gate Designs

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating

A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

An All-MOSFET Sub-1-V Voltage Reference With a−51-dB PSR up to 60 MHz

A 65-nm CMOS Constant Current Source with Reduced PVT Variation

A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy

Preweighted Linearized VCO Analog-to-Digital Converter

A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression

Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template

On Micro-architectural Mechanisms for Cache Wear out Reduction

Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology

A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing

A 30-W 90% Efficiency Dual-Mode Controlled DC–DC Controller With Power Over Ethernet Interface for Power Device

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer- Coupled Technique for SerDes Interface

A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling

A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory

A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Application

A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator

A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive Slope Generator With Hysteresis Voltage Comparison Techniques

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL

A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders

A Novel Photosensitive Tunneling Transistor for Near-Infrared Sensing Applications: Design, Modeling, and Simulation

A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications

A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems

Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms

Aging-Aware Reliable Multiplier Design with Adaptive Hold Logic

Algorithm and Architecture Design of the H.265/HEVC Intra Encoder

All Digital Energy Sensing for Minimum Energy Tracking

An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders

An Efficient Constant Multiplier Architecture Based on Vertical- Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

An Efficient List Decoder Architecture for Polar Codes

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

Architecture for Monitoring SET Propagation in 16-bit Sklansky Adder

Area-Efficient 3-Input Decimal Adders Using Simplified Carry and Sum Vectors

Comparative Performance Analysis of the Dielectrically Modulated Full-Gate and Short-Gate Tunnel FET-Based Biosensors

Design and Analysis of Inexact Floating-Point Adders

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

Design of Efficient Content Addressable Memories in High- Performance FinFET Technology

Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging

Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA

Energy Consumption of VLSI Decoders

Exact and Approximate Algorithms for the Filter Design Optimization Problem

Fast Code Design for Overloaded Code-Division Multiplexing Systems

Fine-Grained Access Management in Reconfigurable Scan Networks

FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

Graph-Based Transistor Network Generation Method for Supergate Design

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

Implementation of Subthreshold Adiabatic Logic for Ultralow- Power Application

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

Integrating Lock-Free and Combining Techniques for a Practical and Scalable FIFO Queue

Learning Weighted Lower Linear Envelope Potentials in Binary Markov Random Fields

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

Long-Distance Measurement Applying Two High-Stability and Synchronous Wavelengths

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

MAC With Action-Dependent State Information at One Encoder

Minimum Parallel Binary Adders with NOR (NAND) Gates

Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder

Modulation Classification of Single-Input Multiple-Output Signals Using Asynchronous Sensors

Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System

Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications

Obfuscating DSP Circuits via High-Level Transformations

One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes

Partially Parallel Encoder Architecture for Long Polar Codes

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

Range Unlimited Delay-Interleaving and –Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit

Recursive Approach to the Design of a Parallel Self-Timed Adder

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI

Shift Register Design Using Two Bit Flip-Flop

Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception

Synthesis of Genetic Clock with Combinational Biologic Circuits

Timing Error Tolerance in Small Core Designs for SoC Applications

Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters

VLSI-Assisted Non-rigid Registration Using Modified Demons Algorithm

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